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+++ SCIOPTA BLOG ARCHIVE 2013 +++ SCIOPTA BLOG ARCHIVE 2013 +++ SCIOPTA BLOG ARCHIVE 2013 +++
BLOG ARCHIVE
  Posted: July 23, 2013 by Roland
ZYNQ-7000 SCIOPTA RTOS for Xilinx Zynq®-7000

SCIOPTA Systems AG has ported the safety certified SCIOPTA Real-Time Operating Systems to the Xilinx Zynq®-7000 All Programmable System-on-Chip.

The SCIOPTA ZYNQ-7000 RTOS is written in highly optimized assembler and specifically tuned for the Cortex-A9 CPUs included in ZYNQ-7000. This results in a very high performance and a low memory footprint.
SCIOPTA ZYNQ-7000 is certified according to IEC61508 SIL3, EN 50128 SIL3/4 and ISO 26262 ASIL D.

Beside the fast Real-Time Kernel there is IPS (Internet Protocols, TCP/IP), IPS Applications (Web Server, DHCP, DNS, SMTP, Telnet, TFTP etc.), SFFS (Flash File Systems), USB support, embedded GUI graphics support and the DRUID System Level Debugger available.

SCIOPTA is royalty free and supports actually the C/C++ compilers and environments from GNU GCC and IAR Systems Embedded Workbench. A pre-compiled version of GCC is included on the SCIOPTA CD.


Xilinx Zynq®-7000 SoCs

Xilinx Zynq®-7000 All Programmable SoC devices fuse a fast processor system (PS) based on two 1GHz ARM Cortex™-A9 MPCore processors with the industry’s fastest and most advanced 28nm programmable logic (PL) fabric, a large on-chip memory, multiple high-speed serial transceivers, numerous hardened peripheral IP cores including DDR and Flash memory controllers, and an on-chip analog-processing block that incorporates two 1Msamples/sec A/D converters.

Memory performance plays a significant role in total system performance and the Zynq-7000 platform features the largest on-chip memory (OCM) and the fastest SDRAM memory controllers available.

On chip, the Zynq-7000 platform includes a high-performance 256Kbyte SRAM OCM. This memory is “tightly coupled” to the ARM processor cores through the Snoop Control Unit at the same hierarchy level as the L2 cache. That means that the processors access the OCM very quickly.

An entire RTOS can fit in this large OCM, which results in very fast system performance. The tightly coupled OCM is especially useful for code that must run very fast or with very low interrupt latency, such as interrupt-service routines. Tightly coupled OCM is also useful for tasks such as cryptography that can be very sensitive to latency and timing variations caused by cache misses.

The Zynq-7000 All Programmable SoC’s Processor System (PS) consists of the following: A 1GHz, dual-core ARM Cortex-A9 MPCore microprocessor and AMBA AXI-based interconnect to communicate with: On-chip memory and External SDRAM and FLASH memory controllers

The on-chip PS is attached to the Zynq-7000 All Programmable SoC’s on-chip Programmable Logic (PL) through 9 AMBA AXI ports and 1 multiplexed I/O port for a total of 3000 signal lines.

  Posted: February 8, 2013 by Roland
MPC8641D SCIOPTA RTOS for Freescale's® MPC8641D Microprocessor

SCIOPTA Systems AG is announcing the immediate availability of the SCIOPTA Real-Time Operating Systems for the MPC8641D processor.

The SCIOPTA MPC5643L RTOS is written in highly optimized assembler and specifically tuned for the MPC8641D processors. This results in a very high performance and a low memory footprint. The MPC86xx kernel is Power ArchitectureTM Book E-compliant (e600 core).

SCIOPTA MPC5643L is certified according to IEC61508 up to SIL3.

Beside the fast Real-Time Kernel there is IPS (Internet Protocols, TCP/IP), IPS Applications (Web Server, DHCP, DNS, SMTP, Telnet, TFTP etc.), SFFS (Flash File Systems), USB support, embedded GUI graphics support and the DRUID System Level Debugger available.

SCIOPTA is royalty free and supports actually the C/C++ compilers and environments from GNU GCC and Windriver/DIAB. A precompiled version of GCC is included on the SCIOPTA CD.


Freescale's® MPC8641D

The MPC8641D uses two high-performance superscalar e600 cores running at up to 1.5 GHz. This three-issue machine has a compact 7-stage pipeline which is particularly efficient with code that branches unpredictably. It avoids the extensive delays associated with flushing a long pipeline on mispredicted branches . Unpredictable branching is typical of code paths driven by largely random arrival of different types of packets. These processors support up to 8 out-of-order instructions on the system bus that allows for making forward progress even while waiting for previous instructions to finish (ie, access to main memory required). The e600 has an on-board 128-bit vector processor for efficient data movement (useful for copying TCP payloads from kernel space to user space) and for math functions that rival a DSP.

The device has dual 64 bit (72b with ECC) DDR2 memory controllers to match the bandwidth requirements of the two cores. The memory controllers can be assigned to each core for increased OS isolation, or can be shared between the cores to ensure the most efficient usage of the memory bandwidth.

There are two flexible high-performance I/O ports. Dual 8-lane PCI Express ports leverage PCI legacy with a high-performance serial point-to-point link that is commonly used to connect to a variety of other on-board high-performance devices. The 4-lane serial RapidIO port, with its low software overhead, configuration simplicity, hardware error correction, and support for both memory mapped and packet-based transactions, is very well suited as a backplane interface.

There are four Ethernet controllers, supporting 10 Mbps, 100 Mbps, and 1000 Mbps. The Ethernet controllers have advanced capabilities for TCP and UPD checksum acceleration, QoS support, and packet header manipulation.

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